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JEDEC is the global leader in developing open standards for the microelectronics industry. With over 4,000 volunteers representing nearly 300 member companies. JEDEC brings manufacturers and suppliers together on 50 different committees, creating standards to meet the diverse technical and developmental needs of the industry. These collaborations ensure product interoperability, benefiting the industry and ultimately consumers by decreasing time-to-market and reducing product development costs.
GUIDELINES FOR PARTICLE IMPACT NOISE DETECTION (PIND) TESTING, OPERATOR TRAINING, AND CERTIFICATION
$39.00 $78.00
TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR MICROELECTRONIC DEVICES
$81.00 $163.00
FBDIMM STANDARD: DDR2 SDRAM FULLY BUFFERED DIMM (FBDIMM) DESIGN SPECIFICATION
$95.00 $191.00
MULTIMEDIACARD (MMC) MECHANICAL STANDARD
$33.00 $67.00
MULTIMEDIACARD (MMC) ELECTRICAL STANDARD, HIGH CAPACITY (MMCA, 4.2)
$104.00 $208.00
DDR2 DIMM CLOCK SKEW MEASUREMENT PROCEDURE USING A CLOCK REFERENCE BOARD
$36.00 $72.00
ADDENDUM No. 11A.01 to JESD8 - 1.5 V +/- 0.1 V (NORMAL RANGE) AND 0.9 - 1.6 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS
$26.00 $53.00
DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS
$37.00 $74.00
STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERSFOR REGISTERED DDR2 DIMM APPLICATIONS
$31.00 $62.00
CYCLED TEMPERATURE HUMIDITY BIAS LIFE TEST
DEFINITION OF THE SSTUA32S865 AND SSTUA32D865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
EARLY LIFE FAILURE RATE CALCULATION PROCEDURE FOR SEMICONDUCTOR COMPONENTS
