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JEDEC is the global leader in developing open standards for the microelectronics industry. With over 4,000 volunteers representing nearly 300 member companies. JEDEC brings manufacturers and suppliers together on 50 different committees, creating standards to meet the diverse technical and developmental needs of the industry. These collaborations ensure product interoperability, benefiting the industry and ultimately consumers by decreasing time-to-market and reducing product development costs.
STANDARD LOGNORMAL ANALYSIS OF UNCENSORED DATA, AND OF SINGLY RIGHT -CENSORED DATA UTILIZING THE PERSSON AND ROOTZEN METHOD
$38.00 $76.00
ADDENDUM No. 8 to JESD24 - METHOD FOR REPETITIVE INDUCTIVE LOAD AVALANCHE SWITCHING
$25.00 $51.00
ADDENDUM No. 9 to JESD24 - SHORT CIRCUIT WITHSTAND TIME TEST METHOD
CMOS SEMICUSTOM DESIGN GUIDELINES
$70.00 $141.00
ADDENDUM No. 2 to JESD24 - GATE CHARGE TEST METHOD
$26.00 $53.00
ADDENDUM No. 6 to JESD12 - INTERFACE STANDARD FOR SEMICUSTOM INTEGRATED CIRCUITS
$27.00 $54.00
ADDENDUM No. 3 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR VERTICAL POWER MOSFETS (DELTA SOURCE-DRAIN VOLTAGE METHOD)
$29.00 $59.00
STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES
$95.00 $191.00
ADDENDUM No. 5 to JESD24 - SINGLE PULSE UNCLAMPED INDUCTIVE SWITCHING (UIS) AVALANCHE TEST METHOD
$24.00 $48.00
ADDENDUM No. 4 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR BIPOLAR TRANSISTORS (DELTA BASE-EMITTER VOLTAGE METHOD)
$28.00 $56.00
ADDENDUM No. 1 to JESD24 - METHOD FOR MEASUREMENT OF POWER DEVICE TURN-OFF SWITCHING LOSS
POWER MOSFET ELECTRICAL DOSE RATE TEST METHOD
