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International Electrotechnical Commission, 07/01/2021
Publisher: IEC
File Format: PDF
$256.00$512.00
Published:01/07/2021
Pages:1320
File Size:1 file , 16 MB
Note:This product is unavailable in Ukraine, Russia, Belarus
The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.
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