The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.
More IEC standard pdf
IEC 60335-2-9 Ed. 6.1 b:2012
Household and similar electrical appliances - Safety - Part 2-9: Particular requirements for grills, toasters and similar portable cooking appliances CONSOLIDATED EDITION
$176.00 $352.00
IEC 60335-2-54 Amd.1 Ed. 3.0 b:2005
Amendment 1 - Household and similar electrical appliances - Safety - Part 2-54: Particular requirements for surface-cleaning appliances for household use employing liquids or steam
$10.00 $21.00
IEC 60371-3-7 Amd.1 Ed. 1.0 en:2006
Amendment 1 - Insulating materials based on mica - Part 3: Specifications for individual materials - Sheet 7: Polyester film mica paper with an epoxy resin binder for single conductor taping
$10.00 $21.00
IEC 60870-6-601 Ed. 1.0 b:1994
Telecontrol equipment and systems - Part 6: Telecontrol protocol s compatible with ISO standards and ITU-T recommendations - Sect ion 601: Functional profile for providing the connection-oriente d transport service in an end system connected via permanent acc ess to a packet switched data network
$47.00 $95.00