IEEE 1364.1-2002

IEEE Standard for Verilog Register Transfer Level Synthesis

IEEE, 12/18/2002

Publisher: IEEE

File Format: PDF

$98.00$196.00

Description

Published:18/12/2002

Pages:108

File Size:1 file , 520 KB

Note:This product is unavailable in Russia, Belarus

To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.

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