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  • IEEE 1450.2-2002

IEEE 1450.2-2002

IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450-1999) for DC Level Specification

IEEE, 03/18/2003

Publisher: IEEE

File Format: PDF

$98.00$197.00


Published:18/03/2003

Pages:31

File Size:1 file , 410 KB

Note:This product is unavailable in Russia, Belarus

Define structures in STIL for specifying the DC conditions for a device under test. Examples of the DC conditions for device power supplies are: device power supply setup, power sequencing to the device, power supply limiting/clamping. Examples of the DC conditions for commonly used signal references are: VIL, VIH, VOL, VOH, IOL, IOH, VREF, VClampLow, VClampHi. Define structures in STIL such that the DC conditions may be specified either globally, by pattern burst, by pattern, or by vector. Define structures in STIL to allow specification of alternate DC levels. Examples of commonly used alternate levels are: VIHH, VIPP, VILL. Define structures in STIL such that the DC levels and alternate levels can be selected within a period, much the same as timed format events.

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