JEDEC JEP001-2A

FOUNDRY PROCESS QUALIFICATION GUIDELINES - FRONT END TRANSISTOR LEVEL (Wafer Fabrication Manufacturing Sites)

JEDEC Solid State Technology Association, 09/01/2018

Publisher: JEDEC

File Format: PDF

$39.00$78.00

Description

Published:01/09/2018

Pages:36

File Size:1 file , 480 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

JEDEC JEP001-2A describes transistor-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation.

More JEDEC standard pdf

JEDEC JESD 24-9 (R2002)

ADDENDUM No. 9 to JESD24 - SHORT CIRCUIT WITHSTAND TIME TEST METHOD

$25.00 $51.00

JEDEC JEP116

CMOS SEMICUSTOM DESIGN GUIDELINES

$70.00 $141.00

JEDEC JES 2

TRANSISTOR, GALLIUM ARSENIDE POWER FET, GENERIC SPECIFICATION

$45.00 $91.00

JEDEC JESD 24-2 (R2002)

ADDENDUM No. 2 to JESD24 - GATE CHARGE TEST METHOD

$26.00 $53.00