• Your shopping cart is empty!

  • JEDEC JEP119A

JEDEC JEP119A

A PROCEDURE FOR EXECUTING SWEAT

JEDEC Solid State Technology Association, 08/01/2003

Publisher: JEDEC

File Format: PDF

$37.00$74.00


Published:01/08/2003

Pages:32

File Size:1 file , 270 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a separate iterative technique (not provided) to calculate the force current for a given target time to failure. This document does not specify what test structure to use with this procedure. However, users of this algorithm report its effectiveness on both straight-lines and via-terminated test structures. Some test-structures design features are provided in JESD87 and in ASTM 1259M - 96.

More JEDEC standard pdf

JEDEC JESD22-B117A

JEDEC JESD22-B117A

SOLDER BALL SHEAR

$28.00 $56.00

JEDEC JESD89A

JEDEC JESD89A

MEASUREMENT AND REPORTING OF ALPHA PARTICLE AND TERRESTRIAL COSMIC RAY INDUCED SOFT ERRORS IN SEMICONDUCTOR DEVICES

$70.00 $141.00

JEDEC JESD82-14A

JEDEC JESD82-14A

DEFINITION OF THE SSTUB32868 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

$37.00 $74.00

JEDEC JESD8-7A

JEDEC JESD8-7A

ADDENDUM No. 7 to JESD8 - 1.8 V + -0.15 V (NORMAL RANGE), AND 1.2 V - 1.95 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUIT

$27.00 $54.00