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JEDEC Solid State Technology Association, 05/01/2002
Publisher: JEDEC
File Format: PDF
$107.00$214.01
Published:01/05/2002
Pages:29
File Size:1 file , 410 KB
Note:This product is unavailable in Russia, Belarus
STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC
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ADDENDUM No. 2 to JESD8 - STANDARD FOR OPERATING VOLTAGES AND INTERFACE LEVELS FOR LOW VOLTAGE EMITTER-COUPLED LOGIC (ECL) INTEGRATED CIRCUITS
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CONDITIONS FOR MEASUREMENT OF DIODE STATIC PARAMETERS
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GUIDELINES FOR GaAs MMIC AND FET LIFE TESTING
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