• JEDEC JEP147

JEDEC JEP147

PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA)

JEDEC Solid State Technology Association, 10/01/2003

Publisher: JEDEC

File Format: PDF

$26.00$53.00


Published:01/10/2003

Pages:11

File Size:1 file , 260 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This procedure describes a recommended way to measure pin capacitance of devices with SSTL (Stub Series Terminated Logic) interface pins by use of a Vector Network Analyzer. One purpose of this standard procedure is to reduce the lengthy and often inaccurate footnote - usually found around the specification of pin parasitics - to a simple reference to this document. In special cases modifying statements may adjust this procedure to the special needs of certain component.

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