JEDEC JEP156A

CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION

JEDEC Solid State Technology Association, 03/01/2018

Publisher: JEDEC

File Format: PDF

$33.00$67.00

Description

Published:01/03/2018

Pages:24

File Size:1 file , 85 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products.

More JEDEC standard pdf

JEDEC JEP128

GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTING

$25.00 $51.00

JEDEC JESD8-8

ADDENDUM No. 8 to JESD8 - STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS

$29.00 $59.00

JEDEC JESD51-3

LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES

$26.00 $53.00

JEDEC EIA 318-B

MEASUREMENT OF REVERSE RECOVERY TIME FOR SEMICONDUCTOR SIGNAL DIODES

$29.00 $59.00