• Your shopping cart is empty!

PDF Preview

JEDEC JEP156A

CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION

JEDEC Solid State Technology Association, 03/01/2018

Publisher: JEDEC

File Format: PDF

$33.00$67.00


Published:01/03/2018

Pages:24

File Size:1 file , 85 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products.

More JEDEC standard pdf

JEDEC JESD91B

JEDEC JESD91B

Method for Developing Acceleration Models for Electronic Device Failure Mechanisms

$30.00 $60.00

JEDEC JEP157A

JEDEC JEP157A

Recommended ESD-CDM Target Levels

$104.00 $208.00

JEDEC JEP151A

JEDEC JEP151A

Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices

$115.00 $230.68

JEDEC JESD78F

JEDEC JESD78F

IC LATCH-UP TEST

$128.00 $256.45