JEDEC JEP156A

CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION

JEDEC Solid State Technology Association, 03/01/2018

Publisher: JEDEC

File Format: PDF

$33.00$67.00


Published:01/03/2018

Pages:24

File Size:1 file , 85 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products.

More JEDEC standard pdf

JEDEC JESD15-1.01

JEDEC JESD15-1.01

COMPACT THERMAL MODEL OVERVIEW

$114.00 $229.40

JEDEC JS-001-2023

JEDEC JS-001-2023

ESDA/JEDEC Joint Standard for Electrostatic Discharge Sensitivity Testing - Human Body Modal (HBM) - Component Level

$101.00 $202.34

JEDEC JESD 82-22.01

JEDEC JESD 82-22.01

INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINES

$23.00 $46.00

JEDEC JESD82-24.01

JEDEC JESD82-24.01

DEFINITION OF the SSTUB32865 28-bit 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

$147.00 $295.38