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  • JEDEC JEP158

JEDEC JEP158

3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactions

JEDEC Solid State Technology Association, 11/01/2009

Publisher: JEDEC

File Format: PDF

$31.00$62.00


Published:01/11/2009

Pages:23

File Size:1 file , 170 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies.

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