JEDEC JEP163

This publication is intended as a guideline to develop and establish conditions for burn-in and life test of MIL-PRF-38535 QML integrated circuits. These guidelines are intended to provide manufacturers with a consistent means of defining burn-in and life test stress and electrical test requirements acceptable to user organizations and for the development of Standard Military Drawings.
The guidelines cover the entire design, wafer fabrication and manufacturing flows, including design and process awareness. Without design awareness (critical circuit blocks/functionality, etc.), burn-in/life test of an integrated circuit might be compromised, or it might dramatically shorten the device’s life prior to system use.