• Your shopping cart is empty!

  • JEDEC JEP171

JEDEC JEP171

GDDR5 Measurement Procedures

JEDEC Solid State Technology Association, 2014

Publisher: JEDEC

File Format: PDF

$38.00$76.00


Pages:34

File Size:1 file , 3 MB

Note:This product is unavailable in Russia, Ukraine, Belarus

This publication is to inform all industry participants of a unified procedure to enable consistent measurement across the industry. This document contains the measurement procedures for testing GDDR5.

This document provides the test methodology details on:
  • CK and WCK Timings: tCK, tWCK, tCH/tCL, tWCKH/tWCKL, CK TJ/RJrms, CK and WCK Jitter
  • CK and WCK Input Operating Conditions: VIXCK, VIXWCK, VIDCK(ac), VIDWCK(ac), VIDCK(dc), VIDWCK(dc), CKslew, and WCKslew
  • Data Input Timings: tDIVW, tDIPW
Note: The procedures described in this document are intended to provide information about the tests that will be used in JEDEC GDDR5 recommended measurement parameter. This testing is not a replacement for an exhaustive test validation plan.

More JEDEC standard pdf

JEDEC JESD22-A109B

JEDEC JESD22-A109B

HERMETICITY

$24.00 $48.00

JEDEC JESD78D

JEDEC JESD78D

IC LATCH-UP TEST

$37.00 $74.00

JEDEC JEP122G

JEDEC JEP122G

FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES

$81.00 $163.00

JEDEC JESD79-3-2

JEDEC JESD79-3-2

Addendum No. 2 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, and DDR3L-1600

$29.00 $59.00