JEDEC JEP69-B (R1999)

PREFERRED LEAD CONFIGURATION FOR FIELD-EFFECT TRANSISTORS

JEDEC Solid State Technology Association, 11/01/1973

Publisher: JEDEC

File Format: PDF

$24.00$48.00

Published:01/11/1973

Pages:8

File Size:1 file , 87 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This publication indicates preferred pinouts for FETs in various package designs.

CHIP CARRIER PINOUTS STANDARDIZED FOR CMOS 4000, HC AND HCT SERIES OF LOGIC CIRCUITS

$26.00 $53.00

DEFINITION OF EXTERNAL CLEARANCE AND CREEPAGE DISTANCES OF DISCRETE SEMICONDUCTOR PACKAGES FOR THYRISTORS AND RECTIFIER DIODES

$24.00 $48.00

LIST OF PREFERRED VALUES FOR USE ON VARIOUS TYPES OF SMALL SIGNAL AND REGULATOR DIODES

$24.00 $48.00

DIGITAL BIPOLAR LOGIC PINOUTS FOR CHIP CARRIERS

$26.00 $53.00