JEDEC JEP69-B (R1999)

PREFERRED LEAD CONFIGURATION FOR FIELD-EFFECT TRANSISTORS

JEDEC Solid State Technology Association, 11/01/1973

Publisher: JEDEC

File Format: PDF

$24.00$48.00

Published:01/11/1973

Pages:8

File Size:1 file , 87 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This publication indicates preferred pinouts for FETs in various package designs.

REFERENCE GUIDE TO LETTER SYMBOLS FOR SEMICONDUCTOR DEVICES

$58.00 $116.00

GUIDELINE FOR ASSESSING THE CURRENT-CARRYING CAPABILITY OF THE LEADS IN A POWER PACKAGE SYSTEM

$26.00 $53.00

COPLANARITY TEST FOR SURFACE-MOUNT SEMICONDUCTOR DEVICES

$26.00 $53.00

SILICON RECTIFIER DIODES

$114.00 $228.00