• Your shopping cart is empty!

  • JEDEC JESD 12-3

JEDEC JESD 12-3

ADDENDUM No. 3 to JESD12 - CMOS GATE ARRAY MACROCELL STANDARD

JEDEC Solid State Technology Association, 06/01/1986

Publisher: JEDEC

File Format: PDF

$29.00$59.00


Published:01/06/1986

Pages:18

File Size:1 file

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard defines a minimum set of macro cell standards for CMOS gate arrays. A total of 41 macro cell types are addressed, all of which are commonly used by gate array designers to implement Application Specific Integrated Circuits.

More JEDEC standard pdf

JEDEC JESD 36

JEDEC JESD 36

STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES

$28.00 $56.00

JEDEC JESD55

JEDEC JESD55

STANDARD FOR DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE BiCMOS LOGIC DEVICES

$31.00 $62.00

JEDEC JEP126

JEDEC JEP126

GUIDELINE FOR DEVELOPING AND DOCUMENTING PACKAGE ELECTRICAL MODELS DERIVED FROM COMPUTATIONAL ANALYSIS

$24.00 $48.00

JEDEC JESD54

JEDEC JESD54

STANDARD FOR DESCRIPTION OF 54/74ABTXXX AND 74BCXXX TTL-COMPATIBLE BiCMOS LOGIC DEVICES

$39.00 $78.00