• Your shopping cart is empty!

  • JEDEC JESD 22-A117B

JEDEC JESD 22-A117B

ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST

JEDEC Solid State Technology Association, 03/01/2009

Publisher: JEDEC

File Format: PDF

$31.00$62.00


Published:01/03/2009

Pages:22

File Size:1 file , 170 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This method establishes a standard procedure for determining the data cycling endurance and data retention capability of non-volatile memory cells. It is intended as a qualification and monitor test procedure. This test is also applicable to FLASH EEPROM integrated circuits and Erasable Programmable Logic Devices (EPLD) with embedded EEPROM or FLASH memory.

More JEDEC standard pdf

JEDEC JESD57

JEDEC JESD57

TEST PROCEDURE FOR THE MANAGEMENT OF SINGLE-EVENT EFFECTS IN SEMICONDUCTOR DEVICES FROM HEAVY ION IRRADIATION

$43.00 $87.00

JEDEC JESD 24-11 (R2002)

JEDEC JESD 24-11 (R2002)

ADDENDUM No. 11 to JESD24 - POWER MOSFET EQUIVALENT SERIES GATE RESISTANCE TEST METHOD

$24.00 $48.00

JEDEC JEP128

JEDEC JEP128

GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTING

$25.00 $51.00

JEDEC JESD8-8

JEDEC JESD8-8

ADDENDUM No. 8 to JESD8 - STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS

$29.00 $59.00