• JEDEC JESD 35-1

JEDEC JESD 35-1

ADDENDUM No. 1 to JESD35 - GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS

JEDEC Solid State Technology Association, 09/01/1995

Publisher: JEDEC

File Format: PDF

$33.00$67.00


Published:01/09/1995

Pages:26

File Size:1 file , 1 MB

Note:This product is unavailable in Russia, Ukraine, Belarus

This addendum expands the usefulness of the Standard 35 (JESD35) by detailing the various sources of measurement error that could effect the test results obtained by the ramped tests described in JESD35. Each source of error is described and its implications on test structure design is noted. This addendum can be used as a guide when designing test structures for the qualification and characterization of thin oxide reliability, specifically, by implementing accelerated voltage or current ramp tests.

More JEDEC standard pdf

JEDEC JESD8-12A.01

JEDEC JESD8-12A.01

1.2 V +/- 0.1 V (NORMAL RANGE) AND 0.8 - 1.3 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS

$26.00 $53.00

JEDEC JESD 8-11A.01

JEDEC JESD 8-11A.01

ADDENDUM No. 11A.01 to JESD8 - 1.5 V +/- 0.1 V (NORMAL RANGE) AND 0.9 - 1.6 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS

$26.00 $53.00

JEDEC JESD8C.01

JEDEC JESD8C.01

INTERFACE STANDARD FOR NOMINAL 3.0 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS

$28.00 $56.00

JEDEC JESD8-14A.01

JEDEC JESD8-14A.01

1.0 V +/- 0.1 V (NORMAL RANGE) AND 0.7 V - 1.1 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS

$26.00 $53.00