• JEDEC JESD 35-1

JEDEC JESD 35-1

ADDENDUM No. 1 to JESD35 - GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS

JEDEC Solid State Technology Association, 09/01/1995

Publisher: JEDEC

File Format: PDF

$33.00$67.00


Published:01/09/1995

Pages:26

File Size:1 file , 1 MB

Note:This product is unavailable in Russia, Ukraine, Belarus

This addendum expands the usefulness of the Standard 35 (JESD35) by detailing the various sources of measurement error that could effect the test results obtained by the ramped tests described in JESD35. Each source of error is described and its implications on test structure design is noted. This addendum can be used as a guide when designing test structures for the qualification and characterization of thin oxide reliability, specifically, by implementing accelerated voltage or current ramp tests.

More JEDEC standard pdf

JEDEC JESD22-B113B

JEDEC JESD22-B113B

BOARD LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF SMT ICS FOR HANDHELD ELECTRONIC PRODUCTS

$33.00 $67.00

JEDEC JEP131C

JEDEC JEP131C

Potential Failure Mode and Effects Analysis (FMEA)

$36.00 $72.00

JEDEC JESD47K

JEDEC JESD47K

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

$38.00 $76.00

JEDEC JESD250A

JEDEC JESD250A

Graphics Double Data Rate (GDDR6) SGRAM Standard

$114.00 $228.00