• JEDEC JESD 35-A

JEDEC JESD 35-A

PROCEDURE FOR WAFER-LEVEL-TESTING OF THIN DIELECTRICS

JEDEC Solid State Technology Association, 03/01/2010

Publisher: JEDEC

File Format: PDF

$43.00$87.00


Published:01/03/2010

Pages:47

File Size:1 file , 680 KB

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The revised JESD35 is intended for use in the MOS Integrated Circuit manufacturing industry. It describes procedures developed for estimating the overall integrity and reliability of thin gate oxides. Three basic test procedures are described, the Voltage-Ramp (V-Ramp), the Current-Ramp (J-Ramp) and the new Constant Current (Bounded J-Ramp) test. Each test is designed for simplicity, speed and ease of use. The standard has been updated to include breakdown criteria that are more robust in detecting breakdown in thinner gate oxides that may not experience hard thermal breakdown.

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