JEDEC JESD 36

STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES

JEDEC Solid State Technology Association, 06/01/1996

Publisher: JEDEC

File Format: PDF

$28.00$56.00

Description

Published:01/06/1996

Pages:15

File Size:1 file , 43 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V - tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses.

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