JEDEC JESD 47G.01

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

JEDEC Solid State Technology Association, 04/01/2010

Publisher: JEDEC

File Format: PDF

$33.00$67.00

Description

Published:01/04/2010

Pages:26

File Size:1 file , 240 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.

More JEDEC standard pdf

JEDEC JESD221

Alpha Radiation Measurement in Electronic Materials

$37.00 $74.00

JEDEC JESD22-B114A

Mark Legibility

$28.00 $56.00

JEDEC JESD47I

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

$36.00 $72.00

JEDEC JESD9B

Inspection Criteria for Microelectronic Packages and Covers

$70.00 $141.00