• JEDEC JESD 78C

JEDEC JESD 78C

IC LATCH-UP TEST

JEDEC Solid State Technology Association, 09/01/2010

Publisher: JEDEC

File Format: PDF

$36.00$72.00


Published:01/09/2010

Pages:28

File Size:1 file , 190 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. This specification covers the I-test and the overvoltage latch-up testing of integrated circuits. The purpose of this specification is to establish a method for determining IC latch-up characteristics and to define latch-up failure criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.

More JEDEC standard pdf

JEDEC JESD8-19

JEDEC JESD8-19

POD18 - 1.8 V Pseudo Open Drain I/O

$27.00 $54.00

JEDEC JESD 82-22

JEDEC JESD 82-22

INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINES

$29.00 $59.00

JEDEC JESD8-23

JEDEC JESD8-23

UNIFIED WIDE POWER SUPPLY VOLTAGE RANGE CMOS DC INTERFACE STANDARD FOR NON-TERMINATED DIGITAL INTEGRATED CIRCUITS

$25.00 $51.00

JEDEC JESD86A

JEDEC JESD86A

ELECTRICAL PARAMETERS ASSESSMENT

$26.00 $53.00