• Your shopping cart is empty!

  • JEDEC JESD 8-9B

JEDEC JESD 8-9B

ADDENDUM No. 9B to JESD8 - STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002

JEDEC Solid State Technology Association, 05/01/2002

Publisher: JEDEC

File Format: PDF

$36.00$72.00


Published:01/05/2002

Pages:28

File Size:1 file , 180 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_2 logic switching range, nominally 0 V to 2.5 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. This standard has been developed particularly with the objective of providing a relatively simple upgrade path from MOS push-pull interface designs. The standard is particularly intended to improve operation in situations where busses must be isolated from relatively large stubs.

More JEDEC standard pdf

JEDEC JESD251-1

JEDEC JESD251-1

Addendum No. 1 to JESD251, Optional x4 Quad I/O With Data Strobe

$31.00 $62.00

JEDEC JEP001-2A

JEDEC JEP001-2A

FOUNDRY PROCESS QUALIFICATION GUIDELINES - FRONT END TRANSISTOR LEVEL (Wafer Fabrication Manufacturing Sites)

$39.00 $78.00

JEDEC JEP001-3A

JEDEC JEP001-3A

FOUNDRY PROCESS QUALIFICATION GUIDELINES - PRODUCT LEVEL (Wafer Fabrication Manufacturing Sites)

$36.00 $72.00

JEDEC JEP001-1A

JEDEC JEP001-1A

FOUNDRY PROCESS QUALIFICATION GUIDELINES - BACKEND OF LINE (Wafer Fabrication Manufacturing Sites)

$33.00 $67.00