• Your shopping cart is empty!

  • JEDEC JESD 8-9B

JEDEC JESD 8-9B

ADDENDUM No. 9B to JESD8 - STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002

JEDEC Solid State Technology Association, 05/01/2002

Publisher: JEDEC

File Format: PDF

$36.00$72.00


Published:01/05/2002

Pages:28

File Size:1 file , 180 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_2 logic switching range, nominally 0 V to 2.5 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. This standard has been developed particularly with the objective of providing a relatively simple upgrade path from MOS push-pull interface designs. The standard is particularly intended to improve operation in situations where busses must be isolated from relatively large stubs.

More JEDEC standard pdf

JEDEC JESD89-2A

JEDEC JESD89-2A

TEST METHOD FOR ALPHA SOURCE ACCELERATED SOFT ERROR RATE

$30.00 $60.00

JEDEC JESD8-12A.01

JEDEC JESD8-12A.01

1.2 V +/- 0.1 V (NORMAL RANGE) AND 0.8 - 1.3 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS

$26.00 $53.00

JEDEC JESD 8-11A.01

JEDEC JESD 8-11A.01

ADDENDUM No. 11A.01 to JESD8 - 1.5 V +/- 0.1 V (NORMAL RANGE) AND 0.9 - 1.6 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS

$26.00 $53.00

JEDEC JESD8C.01

JEDEC JESD8C.01

INTERFACE STANDARD FOR NOMINAL 3.0 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS

$28.00 $56.00