JEDEC JESD 82-29A

DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS

JEDEC Solid State Technology Association, 12/01/2010

Publisher: JEDEC

File Format: PDF

$58.00$116.00

Description

Published:01/12/2010

Pages:80

File Size:1 file , 640 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on DDR3/DDR3L/DDR3U RDIMM applications. The purpose is to provide a standard for the SSTE32882 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

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