JEDEC JESD11

CHIP CARRIER PINOUTS STANDARDIZED FOR CMOS 4000, HC AND HCT SERIES OF LOGIC CIRCUITS

JEDEC Solid State Technology Association, 12/01/1984

Publisher: JEDEC

File Format: PDF

$26.00$53.00

Published:01/12/1984

Pages:12

File Size:1 file , 110 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard indicates the procedures used to convert existing DIP and flat packages for digital parts (SSI & MSI) to chip carrier packages.

BOND WIRE MODELING STANDARD

$28.00 $56.00

QUALITY SYSTEM ASSESSMENT (SUPERSEDES JESD39-A)

$40.00 $80.00

THERMAL TEST CHIP GUIDELINE (WIRE BOND TYPE CHIP)

$28.00 $56.00

TEST PROCEDURE FOR THE MANAGEMENT OF SINGLE-EVENT EFFECTS IN SEMICONDUCTOR DEVICES FROM HEAVY ION IRRADIATION

$43.00 $87.00