JEDEC JESD18-A

STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC

JEDEC Solid State Technology Association, 01/01/1993

Publisher: JEDEC

File Format: PDF

$40.00$80.00

Description

Published:01/01/1993

Pages:44

File Size:1 file , 1.2 MB

Note:This product is unavailable in Russia, Ukraine, Belarus

The purpose of this standard is to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. The standard covers specifications for description of '54/74FCTXXXX' series fast CMOS TTL compatible devices.

More JEDEC standard pdf

JEDEC JEP144

GUIDELINE FOR RESIDUAL GAS ANALYSIS (RGA) FOR MICROELECTRONIC PACKAGES

$37.00 $74.00

JEDEC JESD82-5

STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION

$27.00 $54.00

JEDEC JESD73-4

STANDARD FOR DESCRIPTION OF 3877 - 2.5 V, DUAL 5-BIT, 2-PORT, DDR FET SWITCH

$25.00 $51.00

JEDEC JESD 8-9B

ADDENDUM No. 9B to JESD8 - STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002

$36.00 $72.00