JEDEC JESD2

DIGITAL BIPOLAR LOGIC PINOUTS FOR CHIP CARRIERS

JEDEC Solid State Technology Association, 12/01/1982

Publisher: JEDEC

File Format: PDF

$26.00$53.00

Published:01/12/1982

Pages:11

File Size:1 file , 150 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard provides a chip carrier format for digital devices by defining pin functions and locations for 20, 38, 44, 52, and 68-terminal devices.

FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES

$70.00 $141.00

IPC/JEDEC-9703: Mechanical Shock Test Guidelines for Solder Joint Reliability

$43.00 $87.00

ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST

$31.00 $62.00

GUIDELINES FOR SUPPLIER PERFORMANCE RATING

$30.00 $60.00