JEDEC JESD2

DIGITAL BIPOLAR LOGIC PINOUTS FOR CHIP CARRIERS

JEDEC Solid State Technology Association, 12/01/1982

Publisher: JEDEC

File Format: PDF

$26.00$53.00

Published:01/12/1982

Pages:11

File Size:1 file , 150 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard provides a chip carrier format for digital devices by defining pin functions and locations for 20, 38, 44, 52, and 68-terminal devices.

TEST METHODS AND ACCEPTANCE PROCEDURES FOR THE EVALUATION OF POLYMERIC MATERIALS

$100.00 $201.54

Joint JEDEC/ECA Standard: Definition of "Low-Halogen" for Electronic Products

$30.00 $60.00

POD135 - 1.35 V PSEUDO OPEN DRAIN I/O

$33.00 $67.00

DDR4 NVDIMM-N Design Standard

$40.00 $80.00