• JEDEC JESD203

JEDEC JESD203

STANDARD TEST LOADS FOR DUAL-SUPPLY LEVEL TRANSLATION DEVICES

JEDEC Solid State Technology Association, 11/01/2005

Publisher: JEDEC

File Format: PDF

$25.00$51.00


Published:01/11/2005

Pages:9

File Size:1 file , 86 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard defines ac test loads for dual-supply level translation devices. Uniform test loads enable easy comparison of electrical parameters of dual-supply level translation devices across functions, logic families and IC suppliers. This standard is only intended to apply to devices released subsequent to the publication of this document.

More JEDEC standard pdf

JEDEC JESD75

JEDEC JESD75

BALL GRID ARRAY PINOUTS STANDARDIZED FOR 32-BIT LOGIC FUNCTIONS

$24.00 $48.00

JEDEC JESD66 (R2006)

JEDEC JESD66 (R2006)

TRANSIENT VOLTAGE SUPPRESSOR STANDARD FOR THYRISTOR SURGE PROTECTIVE DEVICE

$58.00 $116.00

JEDEC JESD80

JEDEC JESD80

STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES

$24.00 $48.00

JEDEC JESD625-A

JEDEC JESD625-A

REQUIREMENTS FOR HANDLING ELECTROSTATIC-DISCHARGE-SENSITIVE (ESDS) DEVICES

$36.00 $72.00