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JEDEC Solid State Technology Association, 11/01/2022
Publisher: JEDEC
File Format: PDF
$149.00$299.61
Published:01/11/2022
Pages:48
File Size:1 file , 2.2 MB
Note:This product is unavailable in Russia, Ukraine, Belarus
This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures.
BOARD LEVEL DROP TEST METHOD OF COMPONENTS FOR HANDHELD ELECTRONIC PRODUCTS
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STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS
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LEAD INTEGRITY
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