• JEDEC JESD22-A117C

JEDEC JESD22-A117C

ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST

JEDEC Solid State Technology Association, 10/01/2011

Publisher: JEDEC

File Format: PDF

$31.00$62.00


Published:01/10/2011

Pages:22

File Size:1 file , 160 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This stress test is intended to determine the ability of an EEPROM integrated circuit or an integrated circuit with an EEPROM module (such as a microprocessor) to sustain repeated data changes without failure (program/erase endurance) and to retain data for the expected life of the EEPROM (data retention). This Standard specifies the procedural requirements for performing valid endurance and retention tests based on a qualification specification. Endurance and retention qualification specifications (for cycle counts, durations, temperatures, and sample sizes) are specified in JESD47 or may be developed using knowledge-based methods as in JESD94.

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