JEDEC JESD22-B108B

COPLANARITY TEST FOR SURFACE-MOUNT SEMICONDUCTOR DEVICES

JEDEC Solid State Technology Association, 09/01/2010

Publisher: JEDEC

File Format: PDF

$26.00$53.00

Description

Published:01/09/2010

Pages:14

File Size:1 file , 54 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

The purpose of this test is to measure the deviation of the terminals (leads or solder balls) from coplanarity at room temperature for surface-mount semiconductor devices. This test method is applicable for inspection and device characterization. If package warpage or coplanarity is to be characterized at reflow soldering temperatures, then JESD22-B112 should be used.

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