JEDEC JESD22-B109B

FLIP CHIP TENSILE PULL

JEDEC Solid State Technology Association, 07/01/2014

Publisher: JEDEC

File Format: PDF

$28.00$56.00


Published:01/07/2014

Pages:16

File Size:1 file , 72 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

The Flip Chip Tensile Pull Test Method is performed to determine the fracture mode and strength of the solder bump interconnection between the flip chip die and the substrate. It should be used to assess the consistency of the chip join process. This test method is a destructive test.

More JEDEC standard pdf

JEDEC JESD47I

JEDEC JESD47I

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

$36.00 $72.00

JEDEC JESD9B

JEDEC JESD9B

Inspection Criteria for Microelectronic Packages and Covers

$70.00 $141.00

JEDEC JS-001A-2011

JEDEC JS-001A-2011

ELECTROSTATIC DISCHARGE SENSITIVITY TESTING, HUMAN BODY MODEL (HBM) - COMPONENT LEVEL

$135.00 $271.06

JEDEC JESD209-2E

JEDEC JESD209-2E

Low Power Double Data Rate 2 (LPDDR2)

$152.00 $305.00