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JEDEC Solid State Technology Association, 03/01/2016
Publisher: JEDEC
File Format: PDF
$36.00$72.00
Published:01/03/2016
Pages:30
File Size:1 file , 600 KB
Note:This product is unavailable in Russia, Ukraine, Belarus
BUS INTERCONNECT LOGIC (BIC) FOR 1.2 V
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A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIES
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DEFINITION OF THE SSTV16857 2.5 V, 14-BIT SSTL_2 REGISTERED BUFFER FOR DDR DIMM APPLICATIONS
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HIGH TEMPERATURE STORAGE LIFE
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