Your shopping cart is empty!
PDF Preview
JEDEC Solid State Technology Association, 10/01/2022
Publisher: JEDEC
File Format: PDF
$115.00$231.15
Published:01/10/2022
Pages:134
File Size:1 file , 3.2 MB
Note:This product is unavailable in Russia, Ukraine, Belarus
This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations.
EMBEDDED MULTIMEDIACARD (e*MMC)MECHANICAL STANDARD
$27.00 $54.00
STANDARD FOR DEFINITION OF CU877 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS
$30.00 $60.00
STANDARD METHOD FOR MEASURING AND USING THE TEMPERATURE COEFFICIENT OF RESISTANCE TO DETERMINE THE TEMPERATURE OF A METALLIZATION LINE
$39.00 $78.00
POWER AND TEMPERATURE CYCLING
$25.00 $51.00
