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JEDEC Solid State Technology Association, 02/01/2021
Publisher: JEDEC
File Format: PDF
$114.00$228.00
Published:01/02/2021
Pages:202
File Size:1 file , 3.6 MB
Note:This product is unavailable in Russia, Ukraine, Belarus
ADDENDUM No. 1 to JESD12 - TERMS AND DEFINITIONS FOR GATE ARRAYS AND CELL-BASED INTEGRATED CIRCUITS
$30.00 $60.00
STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC
$40.00 $80.00
ADDENDUM No. 2 to JESD8 - STANDARD FOR OPERATING VOLTAGES AND INTERFACE LEVELS FOR LOW VOLTAGE EMITTER-COUPLED LOGIC (ECL) INTEGRATED CIRCUITS
$25.00 $51.00
CONDITIONS FOR MEASUREMENT OF DIODE STATIC PARAMETERS
$23.00 $47.00