• Your shopping cart is empty!

PDF Preview

JEDEC JESD252.01

Serial Flash Reset Signaling Protocol

JEDEC Solid State Technology Association, 04/01/2021

Publisher: JEDEC

File Format: PDF

$26.00$53.00


Published:01/04/2021

Pages:12

File Size:1 file , 340 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin. Item 1775.06.

More JEDEC standard pdf

JEDEC JESD22-A109B

JEDEC JESD22-A109B

HERMETICITY

$24.00 $48.00

JEDEC JESD78D

JEDEC JESD78D

IC LATCH-UP TEST

$37.00 $74.00

JEDEC JEP122G

JEDEC JEP122G

FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES

$81.00 $163.00

JEDEC JESD79-3-2

JEDEC JESD79-3-2

Addendum No. 2 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, and DDR3L-1600

$29.00 $59.00