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  • JEDEC JESD28-A

JEDEC JESD28-A

A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESS

JEDEC Solid State Technology Association, 12/01/2001

Publisher: JEDEC

File Format: PDF

$29.00$59.00


Published:01/12/2001

Pages:18

File Size:1 file , 60 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This document describes an accelerated test for measuring the hot-carrier-induced degradation of a single n-channel MOSFET using dc bias. The purpose of this document is to specify a minimum set of measurements so that valid comparisons can be made between different technologies, IC processes, and process variations in a simple, consistent and controlled way. The measurements specified should be viewed as a starting point in the characterization and benchmarking of the transistor manufacturing process.

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