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JEDEC Solid State Technology Association, 01/01/2022
Publisher: JEDEC
File Format: PDF
$43.00$87.00
Published:01/01/2022
Pages:46
File Size:1 file , 1.1 MB
Note:This product is unavailable in Russia, Ukraine, Belarus
This standard defines the electrical and mechanical requirements for 288-pin, 1.1 Volt (VDD and VDDQ), DDR5 Registered (RDIMM) and Load Reduced (LRDIMM), Double Data Rate (DDR), Synchronous DRAM Dual In-Line Memory Modules (DIMM). These 288-pin Registered and Load Reduced DDR5 SDRAM DIMMs are intended for use in server, workstation, and database environments. Item 2273.07.
STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION
$27.00 $54.00
STANDARD FOR DESCRIPTION OF 3877 - 2.5 V, DUAL 5-BIT, 2-PORT, DDR FET SWITCH
$25.00 $51.00
ADDENDUM No. 9B to JESD8 - STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002
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BEADED THERMOCOUPLE TEMPERATURE MEASUREMENT OF SEMICONDUCTOR PACKAGES