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JEDEC Solid State Technology Association, 06/01/2022
Publisher: JEDEC
File Format: PDF
$145.00$290.40
Published:01/06/2022
Pages:34
File Size:1 file , 910 KB
Note:This product is unavailable in Russia, Ukraine, Belarus
This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM UDIMMs). These DDR5 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in Computers.
Reference design examples are included which provide an initial basis for DDR5 UDIMM designs. Modifications to these reference designs may be required to meet all system timing, signal integrity and thermal requirements for PC5-4000, PC5-4400, PC5-4800 and beyond PC5-6400 support. All DDR5 UDIMM implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the design.
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