JEDEC JESD47H

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

JEDEC Solid State Technology Association, 02/01/2011

Publisher: JEDEC

File Format: PDF

$33.00$67.00

Description

Published:01/02/2011

Pages:26

File Size:1 file , 240 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.

More JEDEC standard pdf

JEDEC JESD217

TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES

$40.00 $80.00

JEDEC JESD 78C

IC LATCH-UP TEST

$36.00 $72.00

JEDEC JESD22-B108B

COPLANARITY TEST FOR SURFACE-MOUNT SEMICONDUCTOR DEVICES

$26.00 $53.00

JEDEC JESD 219

SOLID STATE DRIVE (SSD) ENDURANCE WORKLOADS

$25.00 $51.00