• Your shopping cart is empty!

PDF Preview

JEDEC JESD47I.01

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

JEDEC Solid State Technology Association, 10/01/2016

Publisher: JEDEC

File Format: PDF

$36.00$72.00


Published:01/10/2016

Pages:28

File Size:1 file , 280 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed. This is a minor editorial revision to JESD47I, published December 2015.

More JEDEC standard pdf

JEDEC JESD 82-25

JEDEC JESD 82-25

DEFINITION OF the SSTUB32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

$40.00 $80.00

JEDEC JESD 82-26

JEDEC JESD 82-26

DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS

$37.00 $74.00

JEDEC JESD 82-24

JEDEC JESD 82-24

DEFINITION OF the SSTUB32865 28-bit 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

$36.00 $72.00

JEDEC JESD82-9B

JEDEC JESD82-9B

DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS

$33.00 $67.00