JEDEC JESD47K

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

JEDEC Solid State Technology Association, 08/01/2018

Publisher: JEDEC

File Format: PDF

$38.00$76.00


Published:01/08/2018

Pages:34

File Size:1 file , 660 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.

More JEDEC standard pdf

JEDEC JEP155B

JEDEC JEP155B

RECOMMENDED ESD TARGET LEVELS FOR HBM QUALIFICATION

$45.00 $91.00

JEDEC J-STD-033D

JEDEC J-STD-033D

Handling, Packing, Shipping and Use of Moisture, Reflow, and Process Sensitive Devices

$39.00 $79.00

JEDEC JESD22-A111B

JEDEC JESD22-A111B

EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES

$31.00 $62.00

JEDEC JESD8-31

JEDEC JESD8-31

1.8 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE

$24.00 $48.00