JEDEC JESD47K

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

JEDEC Solid State Technology Association, 08/01/2018

Publisher: JEDEC

File Format: PDF

$38.00$76.00

Description

Published:01/08/2018

Pages:34

File Size:1 file , 660 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.

More JEDEC standard pdf

JEDEC JESD37A

Lognormal Analysis of Uncensored Data, and of Singly Right-Censored Data Utilizing the Persson and Rootzen Method

$38.00 $76.00

JEDEC JESD214.01

CONSTANT-TEMPERATURE AGING METHOD TO CHARACTERIZE COPPER INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING

$36.00 $72.00

JEDEC JESD30H

Descriptive Designation System for Semiconductor-device Packages

$58.00 $116.00

JEDEC JESD250

Graphics Double Data Rate (GDDR6) SGRAM Standard

$114.00 $228.00