JEDEC JESD50C

SPECIAL REQUIREMENTS FOR MAVERICK PRODUCT ELIMINATION AND OUTLIER MANAGEMENT

JEDEC Solid State Technology Association, 01/01/2018

Publisher: JEDEC

File Format: PDF

$30.00$60.00

Description

Published:01/01/2018

Pages:20

File Size:1 file , 300 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard applies to the identification and control of Maverick Product that can occur during fabrication, assembly, packaging, or test of any electronic component. It can be implemented for an entire product line or to segregate product that has a higher probability of adversely impacting quality or reliability.

More JEDEC standard pdf

JEDEC JESD8-4

ADDENDUM No. 4 to JESD8 - CENTER-TAP-TERMINATED (CTT) INTERFACE LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS

$24.00 $48.00

JEDEC JESD 12-1B

ADDENDUM No. 1 to JESD12 - TERMS AND DEFINITIONS FOR GATE ARRAYS AND CELL-BASED INTEGRATED CIRCUITS

$30.00 $60.00

JEDEC JESD18-A

STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC

$40.00 $80.00

JEDEC JESD8-2

ADDENDUM No. 2 to JESD8 - STANDARD FOR OPERATING VOLTAGES AND INTERFACE LEVELS FOR LOW VOLTAGE EMITTER-COUPLED LOGIC (ECL) INTEGRATED CIRCUITS

$25.00 $51.00