Your shopping cart is empty!
JEDEC Solid State Technology Association, 11/01/2012
Publisher: JEDEC
File Format: PDF
$36.00$72.00
Published:01/11/2012
Pages:28
File Size:1 file , 270 KB
Note:This product is unavailable in Russia, Ukraine, Belarus
ADDENDUM No. 11 to JESD24 - POWER MOSFET EQUIVALENT SERIES GATE RESISTANCE TEST METHOD
$24.00 $48.00
GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTING
$25.00 $51.00
ADDENDUM No. 8 to JESD8 - STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
$29.00 $59.00
LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES
$26.00 $53.00