• Your shopping cart is empty!

  • JEDEC JESD51-4

JEDEC JESD51-4

THERMAL TEST CHIP GUIDELINE (WIRE BOND TYPE CHIP)

JEDEC Solid State Technology Association, 02/01/1997

Publisher: JEDEC

File Format: PDF

$28.00$56.00


Published:01/02/1997

Pages:15

File Size:1 file , 310 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This guideline describes design requirements for wire bond type semiconductor chips to be used for thermal resistance listing of IC packages. This document provides specific guidelines for chip design but allows flexibility in the materials and layout requirements.

More JEDEC standard pdf

JEDEC JESD65B

JEDEC JESD65B

DEFINITION OF SKEW SPECIFICATIONS FOR STANDARD LOGIC DEVICES

$30.00 $60.00

JEDEC JESD 31C

JEDEC JESD 31C

GENERAL REQUIREMENTS FOR DISTRIBUTORS OF COMMERCIAL AND MILITARY SEMICONDUCTOR DEVICES

$33.00 $67.00

JEDEC JESD8-15A

JEDEC JESD8-15A

STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18)

$31.00 $62.00

JEDEC JESD92

JEDEC JESD92

PROCEDURE FOR CHARACTERIZING TIME-DEPENDENT DIELECTRIC BREAKDOWN OF ULTRA-THIN GATE DIELECTRICS

$37.00 $74.00