JEDEC JESD51-4A

Thermal Test Chip Guideline (Wire Bond Type Chip)

JEDEC Solid State Technology Association, 06/01/2019

Publisher: JEDEC

File Format: PDF

$33.00$67.00


Published:01/06/2019

Pages:26

File Size:1 file , 1.2 MB

Note:This product is unavailable in Russia, Ukraine, Belarus

The purpose of this document is to provide a design guideline for thermal test chips used for integrated circuit (IC) and transistor package thermal characterization and investigations. The intent of this guideline is to minimize the differences in data gathered due to nonstandard test chips and to provide a well-defined reference for thermal investigations.

More JEDEC standard pdf

JEDEC JESD 353 (R2009)

JEDEC JESD 353 (R2009)

THE MEASUREMENT OF TRANSISTOR NOISE FIGURE AT FREQUENCIES UP TO 20 kHz BY SINUSOIDAL SIGNAL-GENERATOR METHOD

$25.00 $51.00

JEDEC JESD307 (R2002)

JEDEC JESD307 (R2002)

VOLTAGE REGULATOR DIODE NOISE VOLTAGE MEASUREMENT

$24.00 $48.00

JEDEC JEP65 (R1999)

JEDEC JEP65 (R1999)

TEST PROCEDURES FOR VERIFICATION OF MAXIMUM RATINGS OF POWER TRANSISTORS

$33.00 $67.00

JEDEC JESD302 (R2009)

JEDEC JESD302 (R2009)

RANGES AND CONDITIONS FOR SPECIFYING BETA FOR LOW POWER, AUDIO FREQUENCY TRANSISTORS FOR ENTERTAINMENT SERVICE

$23.00 $47.00