Your shopping cart is empty!
PDF Preview
JEDEC Solid State Technology Association, 10/01/2022
Publisher: JEDEC
File Format: PDF
$105.00$210.68
Published:01/10/2022
Pages:12
File Size:1 file , 490 KB
Note:This product is unavailable in Russia, Ukraine, Belarus
The measurement methodology described herein is distributed among several documents so that the appropriate combination of documents can be selected to meet specific thermal measurement requirements. This document provides the OVERVIEW; the rest of the documents are grouped as shown in this chart.
TEST PROCEDURE FOR THE MANAGEMENT OF SINGLE-EVENT EFFECTS IN SEMICONDUCTOR DEVICES FROM HEAVY ION IRRADIATION
$43.00 $87.00
ADDENDUM No. 11 to JESD24 - POWER MOSFET EQUIVALENT SERIES GATE RESISTANCE TEST METHOD
$24.00 $48.00
GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTING
$25.00 $51.00
ADDENDUM No. 8 to JESD8 - STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
$29.00 $59.00
