JEDEC JESD52

STANDARD FOR DESCRIPTION OF LOW VOLTAGE TTL-COMPATIBLE CMOS LOGIC DEVICES

JEDEC Solid State Technology Association, 11/01/1995

Publisher: JEDEC

File Format: PDF

$28.00$56.00

Description

Published:01/11/1995

Pages:15

File Size:1 file , 240 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard describes dc interface specifications and test environment for these devices that operate with 2.7 V to 3.6 V power supplies. The goal is to provide a consistent set of dc specifications for reference by logic suppliers and users alike.

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