• JEDEC JESD55

JEDEC JESD55

STANDARD FOR DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE BiCMOS LOGIC DEVICES

JEDEC Solid State Technology Association, 05/01/1996

Publisher: JEDEC

File Format: PDF

$31.00$62.00


Published:01/05/1996

Pages:22

File Size:1 file , 540 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

The purpose is to provide a standard of BiCMOS Logic series specifications for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users.

More JEDEC standard pdf

JEDEC JEP121A

JEDEC JEP121A

REQUIREMENTS FOR MICROELECTRONIC SCREENING AND TEST OPTIMIZATION

$38.00 $76.00

JEDEC JESD22-B113

JEDEC JESD22-B113

BOARD LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF COMPONENTS FOR HANDHELD ELECTRONIC PRODUCTS

$31.00 $62.00

JEDEC JESD202

JEDEC JESD202

METHOD FOR CHARACTERIZING THE ELECTROMIGRATION FAILURE TIME DISTRIBUTION OF INTERCONNECTS UNDER CONSTANT-CURRENT AND TEMPERATURE STRESS

$30.00 $61.00

JEDEC JP 002

JEDEC JP 002

CURRENT TIN WHISKERS THEORY AND MITIGATION PRACTICES GUIDELINE

$36.00 $72.00