JEDEC JESD60A

A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS

JEDEC Solid State Technology Association, 09/01/2004

Publisher: JEDEC

File Format: PDF

$33.00$67.00

Description

Published:01/09/2004

Pages:24

File Size:1 file , 85 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This method establishes a standard procedure for accelerated testing of the hot-carrier-induced change of a p-channel MOSFET. The objective is to provide a minimum set of measurements so that accurate comparisons can be made between different technologies. The measurements specified should be viewed as a starting pint in the characterization and benchmarking of the trasistor manufacturing process.

More JEDEC standard pdf

JEDEC JS 9704

IPC/JEDEC-9704: Printed Wiring Board (PWB) Strain Gage Test Guideline

$37.00 $74.00

JEDEC JESD 22-A108C

TEMPERATURE, BIAS, AND OPERATING LIFE

$27.00 $54.00

JEDEC JESD 48B

PRODUCT DISCONTINUANCE

$25.00 $51.00

JEDEC JESD 82-13A

DEFINITION OF THE SSTVN16859 2.5-2.6 V 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR PC1600, PC2100, PC2700 AND PC3200 DDR DIMM APPLICATIONS

$29.00 $59.00