• JEDEC JESD61A.01

JEDEC JESD61A.01

ISOTHERMAL ELECTROMIGRATION TEST PROCEDURE

JEDEC Solid State Technology Association, 10/01/2007

Publisher: JEDEC

File Format: PDF

$43.00$87.00


Published:01/10/2007

Pages:49

File Size:1 file , 480 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard describes an algorithm for the execution of the isothermal test, using computer-controlled instrumentation. The primary use of this test is for the monitoring of microelectronic metallization lines at wafer level (1) in process development, to evaluate process options, (2) in manufacturing, to monitor metallization reliability and (3) to monitor/evaluate process equipment. While it is developed as a fast WLR test, it can also be an effective tool for complementing the reliability data obtained through the standard package level electromigration test.

More JEDEC standard pdf

JEDEC JESD8C.01

JEDEC JESD8C.01

INTERFACE STANDARD FOR NOMINAL 3.0 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS

$28.00 $56.00

JEDEC JESD8-14A.01

JEDEC JESD8-14A.01

1.0 V +/- 0.1 V (NORMAL RANGE) AND 0.7 V - 1.1 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS

$26.00 $53.00

JEDEC JESD8-5A.01

JEDEC JESD8-5A.01

ADDENDUM No. 5 to JESD8 - 2.5 V 0.2 V (NORMAL RANGE), AND 1.8 V TO 2.7 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUIT

$27.00 $54.00

JEDEC JESD 88C

JEDEC JESD 88C

DICTIONARY OF TERMS FOR SOLID STATE TECHNOLOGY, FOURTH EDITION

$75.00 $150.00